Architecture
Optimization of Reconfigurable Architectures for Efficient Implementation of Particle Filters
PIs: Petar M. Djuric, Sangjin Hong
The aims of this project are to develop new theoretical and practical approaches for building particle filters. They include balancing of hardware and software, reduction of computational complexities by transformations and approximations, investigation of the degree of parallelism, researching of various interconnection mechanisms, random communication schemes, hardware optimization, and design of low power VLSI processors. Another important effort is building reconfigurable hardware so that it is suitable for different types of particle filters. This work does not only advances the theory and practice of balancing hardware/software and computation/communication in systems architecture but also stimulates great activity in the signal processing community towards solving difficult problems by particle filters. Particularly useful are some case studies such as the problem of bearings-only tracking and various problems in wireless communications. (NSF)
Architecture and Design of 50-100 GHz Superconductor RSFQ Microprocessors for High-End Computing
PI: Mikhail Dorojevets
The recent report titled “High Performance Computing for the National Security Community” prepared by several federal agencies clearly identified the need for user-friendly high-end computing systems with high-bandwidth capabilities because of the existence of critical applications for the national security community “that are neither met nor addressed by the commercial sector”. Superconductor processors based on Rapid Single Flux Quantum (RSFQ) circuit technology can potentially reach and exceed operating frequencies of 100 GHz, while keeping processor power consumption low. In order to be able to initiate the design of a superconductor system for petaflops computing, the following critical design issues need to be addressed: processor microarchitecture, memory, and interconnect. The proposed development program plans to find and demonstrate viable solutions for these architectural, design, and fabrication challenges during the 2006-2010 time frame. (Department of Defense)
High Performance Architectures for Multimedia Applications
PI: Sangjin Hong, Wendy Tang, Alex Doboli
This research is being jointly conducted with investigators at Stony Brook University and investigators at University of Maryland, College Park. The successful project will result in a new type of the processor for many computationally intensive multimedia applications. The core of this research is to develop new way of processing multimedia application by representing multimedia processing algorithms in terms of simple matrix operations. The matrix operations are then transformed into simple arithmetic operations requiring small database access. We are interested in providing hardware mapping methodology to a hardware resource template that corresponds to a basic matrix operation. Ultimately, a rapidly reconfigurable architecture will be developed where it can be integrated by means of co-processing with the general-purpose processors for executing multimedia applications with maximum performance. Since this project considers high-level matrix operations as instruction, the reconfigurable hardware will be able to configure resource very quickly to support high throughput execution. (NSF)
Implantable Neural Interfaces
PI: Milutin Stanacevic
Design of implanted neural interfaces could facilitate understanding of neurological phenomena and allow for automated medical diagnostics. Mixed-signal VLSI solutions offer high sensitivity, low noise, low power and high spatial resolution sensing of neurochemical activity for multi-channel acquisition system that could be integrated with sensor arrays. Passive RF telemetry based on inductive coupling implemented on the same substrate provides data and power transfer. The goal of the project is design of fully integrated stand-alone implanted wireless probe capable of transducing, sensing, processing and transmitting neurochemical signals. (SBU)